A/D converter, method of A/D conversion, and signal processing device

ABSTRACT

When the performance of an A/D converter required by a system changes, power consumption of the overall system can be reduced. The resolution of an A/D converter is made variable by changing a current flowing through an amplifier by an external control signal that specifies the resolution. Thus, when the performance required by a system changes, it is possible to change the performance of the A/D converter and to prevent a performance overhead of the A/D converter. Consequently, power consumption of the A/D converter is reduced, and power consumption of the system as a whole is also reduced.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to analog-to-digital (A/D)converters, methods of A/D conversion, and signal processing devices.

[0002] In the information and communication field, signal processing hasdemanded digital processing, faster speeds, and broader bandwidths, andinformation and communication devices have required reduced sizes andweight. These trends have required A/D converters, which are crucialdevices to the digital signal processing, to have faster speeds, broaderbandwidths, and lower power consumption. Various components in A/Dconverters employ operational amplifiers, each of which serves a veryimportant function. Examples of the operational amplifiers incorporatedin A/D converters include a comparator, which compares a supplied analoginput voltage with a reference voltage, a sample-and-hold circuit, whichperforms a sampling and holding operation of an input signal in order toachieve a faster speed and a broader bandwidth, a differential signalamplifier circuit, which is used for, for example, the signalamplification in a pipeline A/D converter, and the like.

[0003]FIG. 13 shows an example of the differential input-differentialoutput operational amplifier used for A/D converters. The presentcircuit is biased by a constant current source Iss. The gate terminalsof N-channel transistors M1 and M2, which are input transistors, arerespectively connected to an analog differential input signal-positiveelectrode Vin⁺ and an analog differential input signal-negativeelectrode Vin⁻. The source terminals of the N-channel transistors M1 andM2 are connected to a reference voltage VSS. The gate terminals ofP-channel transistors M3 and M4 are connected to a bias voltage Vb. Thesource terminals of the P-channel transistors M3 and M4 are connected toa power supply voltage VDD. The drain terminals of the N-channeltransistor M1 and the P-channel transistor M3 are connected to an analogdifferential output signal-negative electrode Vout⁻. The drain terminalsof the N-channel transistor M2 and the P-channel transistor M4 areconnected to an analog differential output signal-positive electrodeVout⁺.

[0004] By the voltage-current conversion function of the N-channeltransistors M1 and M2, an analog differential input signalΔVin=(Vin⁺−Vin⁻) is converted into a difference current ΔIds between adrain-source current Ids1 that flows in the N-channel transistor M1 anda drain-source current Ids2 that flows in the N-channel transistor M2(ΔIds =(Ids1−Ids2)). The deltas ΔIds1 and AIds2 of the drain-sourcecurrent Ids1 and the drain-source current Ids2 are obtained by thefollowing equations: ΔIds1=gm1(ΔVin/2) and ΔIds2=gm2(ΔVin/2),respectively, where gm1 is the transconductance of the N-channeltransistor M1 and gm2 is the transconductance of the N-channeltransistor M2. Given that the N-channel transistors M1 and M2 have thesame characteristics, gm=gm1=gm2. Where the dynamic resistance of theoutput terminal is denoted by ro, an analog differential output signalΔVout=(ΔVout⁺−ΔVout⁻) is obtained by the following equation:ΔVout=gm·ΔVin·ro. Accordingly, a voltage gain G of the present circuitcan be obtained by the following equation: G=ΔVout/ΔVin=gm·ro.

[0005] In other words, the voltage gain G of the operational amplifieris proportional to the transconductance gm of the N-channel transistorsM1 and M2, which are input transistors. Moreover, the transconductancegm is approximately proportional to the drain-source current Ids flowingin the transistors. Therefore, in order to increase the voltage gain G,it is necessary to increase the drain-source current Ids.

[0006] To achieve a higher-resolution and faster-speed A/D converter, itis necessary to increase precision, gain, and speed of the operationalamplifier.

[0007] Generally, operational amplifiers are operated at a constantcurrent biased state. Accordingly, power consumption of an operationalamplifier is approximately constant at all times.

[0008] As discussed above, in conventional A/D converters, the currentflowing through the operational amplifier that is incorporated in an A/Dconverter does not change, and consequently, the performance of the A/Dconverter per se does not change even when the system requires a changein performance of the A/D converter. Generally, the performance of anA/D converter is approximately correlated with the power consumption.For these reasons, conventional A/D converters have at least thefollowing problem. When the performance of the A/D converter is higherthan the required performance of the A/D converter that is required bythe system (when a performance overhead occurs), the A/D converterconsumes electric power wastefully.

SUMMARY OF THE INVENTION

[0009] In view of the foregoing and other problems, it is an object ofthe present invention to reduce the power consumption of the overallsystem when the system requires a change in the performance of an A/Dconverter.

[0010] This and other objects are accomplished by the following aspectsof the invention. More specifically, in accordance with one aspect, thepresent invention provides an A/D converter wherein its resolution ismade variable by changing a current flowing through an amplifier with acontrol signal that specifies the resolution.

[0011] The invention also provides an A/D converter comprising: acontrolling means for determining a resolution; an amplifier forchanging a current with a signal from the controlling means; and avoltage comparator array to which an output from the amplifier is input;wherein the resolution is corrected by inputting the result of thecomparison in the voltage comparator array into the controlling means.

[0012] In accordance with another aspect, the present invention alsoprovides a signal processing device comprising: the above-described A/Dconverter; a signal processing means in which part of the performance isdetermined by the resolution of the A/D converter; a monitoring meansfor monitoring the performance of the signal processing meansattributable to the resolution of the A/D converter and instructing theA/D converter to increase the resolution if a decrease of theperformance is detected and to reduce the resolution if an overhead ofthe performance is detected. Preferably, the signal processing means isa digital demodulator circuit; and the performance is a bit error rateof the digital demodulator circuit.

[0013] In accordance with further another aspect, the present inventionprovides a method of A/D conversion, comprising: a voltage-inputtingstep of inputting a test voltage in an amplifier; a comparing step ofcomparing the voltage that is output from the amplifier with the testvoltage; and a resolution-determining step of adjusting a current valueof the amplifier according to the result obtained in the comparing step.

[0014] As described above, when the performance required by a systemchanges, the performance of the A/D converter can be changed accordingto the status of the system, and as a consequence, performance overheadscan be prevented in A/D converters. Thus, power consumption of A/Dconverters can be reduced, and accordingly, power consumption of thewhole system can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a schematic diagram of an A/D converter according toEmbodiment 1 of the invention.

[0016]FIG. 2 is a schematic diagram of a signal processing deviceaccording to Embodiment 2 of the invention.

[0017]FIG. 3 is a schematic diagram of a signal processing deviceaccording to Embodiment 3 of the invention.

[0018]FIG. 4 is a schematic diagram of a signal processing deviceaccording to Embodiment 4 of the invention.

[0019]FIG. 5 is a schematic diagram of a signal processing deviceaccording to Embodiment 5 of the invention.

[0020]FIG. 6 is a schematic diagram of an operational amplifier in anA/D converter according to Embodiment 6 of the invention.

[0021]FIG. 7 is a modified example of the operational amplifier of FIG.6.

[0022]FIG. 8 is a schematic diagram of the current mirror circuit as avariable current supply in an A/D converter according to Embodiment 6.

[0023]FIG. 9 is a schematic diagram showing an operational amplifier inan A/D converter according to Embodiment 7 of the invention.

[0024]FIG. 10 is a schematic diagram showing an A/D converter accordingto Embodiment 8 of the invention.

[0025]FIG. 11 is a timing chart of an A/D converter according toEmbodiment 8.

[0026]FIG. 12 shows a voltage comparator array in an A/D converteraccording to Embodiment 8.

[0027]FIG. 13 is a schematic diagram showing an operational amplifier ina conventional A/D converter.

DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinbelow, preferred embodiments of the present invention aredetailed.

[0029] Embodiment 1

[0030]FIG. 1 is a diagram showing the configuration of an A/D converteraccording to Embodiment 1 of the present invention.

[0031] An analog input signal 2 is supplied as input to an A/D converter1 a. The A/D converter 1 a outputs a digital output signal 3 accordingto the analog input signal 2. A control signal 4 is supplied also asinput to the A/D converter 1 a from outside. The A/D converter 1 aaccording to Embodiment of the present invention is thus configured.

[0032] Next, the operation of the A/D converter 1 a according to thepresent embodiment is explained below.

[0033] First, the analog input signal 2 is supplied as input to the A/Dconverter 1 a. The A/D converter 1 a outputs the digital output signal 3according to the analog input signal 2. At this time, the powerconsumption of the A/D converter 1 a is controlled by the control signal4. The power consumption and performance of the A/D converter 1 a areapproximately correlated to each other, and therefore, the performanceof the A/D converter 1 a can be changed by controlling the powerconsumption of the A/D converter 1 a.

[0034] Thus, according to the present embodiment, the power consumptionof the A/D converter 1 a can be changed with the external control signal4, and as a consequence, the performance of the A/D converter 1 a can bechanged. Therefore, it is possible to reduce the power consumption ofthe system as a whole that contains the A/D converter 1 a.

[0035] It should be noted that the control signal 4 may be any of analogsignal, digital signal, or the combinations thereof The conversionsystem of the A/D converter 1 a may be any of flash type, 2-step flashtype, subranging type, successive approximation type, integral type, orpipeline type.

[0036] Embodiment 2

[0037]FIG. 2 is a diagram showing the configuration of a signalprocessing device according to Embodiment 2 of the present invention.

[0038] In FIG. 2, reference character 1 b indicates an A/D converter,reference character 5 b indicates an internal system that operatesindependently of the A/D converter 1 b, and reference character 6 bindicates an external system that incorporates the A/D converter 1 b andthe internal system 5 b inside. An analog input signal 2 is supplied asinput to the A/D converter 1 b from the internal system 5 b. The A/Dconverter 1 b outputs a digital output signal 3 according to the analoginput signal 2. A control signal 4 is supplied also as input to the A/Dconverter 1 b from the internal system 5 b. The signal processing systemaccording to Embodiment 2 of the present invention is thus configured.

[0039] Next, the operation of the signal processing device according tothe present embodiment is described below.

[0040] First, the analog input signal 2 is supplied as input to the A/Dconverter 1 b from the internal system 5 b. The A/D converter 1 boutputs the digital output signal 3 according to the analog input signal2. At the same time, the control signal 4 that contains informationabout the required performance of the A/D converter 1 b is supplied asinput to the A/D converter 1 b from the internal system 5 b. At thistime, the power consumption of the A/D converter 1 b is controlled bythe control signal 4. The power consumption and performance of the A/Dconverter 1 b are approximately correlated to each other, and therefore,the performance of the A/D converter 1 b can be changed by controllingthe power consumption of the A/D converter 1 b.

[0041] Thus, according to the present embodiment, the power consumptionof the A/D converter 1 b can be changed according to the performancethat is required by the system. Therefore, it is possible to reduce thepower consumption of the overall system.

[0042] Embodiment 3

[0043]FIG. 3 is a diagram showing the configuration of a signalprocessing device according to Embodiment 3 of the present invention.

[0044] In FIG. 3, reference character 1 c indicates an A/D converter,reference character 5 c indicates an internal system that operatesindependently of the A/D converter 1 c, and reference character 6 cindicates an external system that incorporates the A/D converter 1 c andthe internal system 5 c inside. An analog input signal 2 is supplied asinput to the A/D converter 1 c from the internal system 5 c. The A/Dconverter 1 c outputs a digital output signal 3 according to the analoginput signal 2. The resulting digital output signal 3 is fed back to theinternal system 5 c. A control signal 4 is supplied also as input to theA/D converter 1 c from the internal system 5 c. The signal processingsystem according to Embodiment 3 of the present invention is thusconfigured.

[0045] Next, the operation of the signal processing device according tothe present embodiment is described below.

[0046] First, the analog input signal 2 is supplied as input to the A/Dconverter 1 c from the internal system 5 c. The A/D converter 1 coutputs the digital output signal 3 according to the analog input signal2. At the same time, the control signal 4 that contains informationabout a required performance of the A/D converter 1 c is supplied asinput to the A/D converter 1 c from the internal system 5 c. Meanwhile,the digital output signal 3 is fed back to the internal system 5 c. Theinternal system 5 c again outputs the control signal 4 according to thedigital output signal 3. The control signal 4 is supplied as input tothe A/D converter 1 c. At this time, the power consumption of the A/Dconverter 1 c is controlled by the control signal 4. The powerconsumption and performance of the A/D converter 1 c are approximatelycorrelated to each other, and therefore, the performance of the A/Dconverter 1 c can be changed by controlling the power consumption of theA/D converter 1 c.

[0047] Thus, according to the present embodiment, the power consumptionof the A/D converter 1 c can be reduced to the minimum level that isrequired by the overall system. Therefore, it is possible to optimizethe power consumption and performance of the A/D converter 1 c andreduce the power consumption of the overall system.

[0048] Embodiment 4

[0049]FIG. 4 is a diagram showing the configuration of a signalprocessing device according to Embodiment 4 of the present invention.

[0050] In FIG. 4, reference character Id indicates an A/D converter,reference character 5 d indicates an internal system that operatesindependently of the A/D converter 1 d, reference character 6 dindicates an external system that incorporates the A/D converter 1 d andthe internal system 5 d inside, and reference character 8 indicates asystem characteristic monitor. An analog input signal 2 is supplied asinput to the A/D converter 1 d from the internal system 5 d. The A/Dconverter 1 d outputs a digital output signal 3 according to the analoginput signal 2. The resulting digital output signal 3 is fed back to theinternal system 5 d. Meanwhile, an internal system characteristic 7 issupplied from the internal system 5 d to the system characteristicmonitor 8. The system characteristic monitor 8 outputs a control signal4 according to the internal system characteristic 7. A control signal 4is supplied as input to the A/D converter Id from the systemcharacteristic monitor 8. The signal processing system according toEmbodiment 4 of the present invention is thus configured.

[0051] Next, the operation of the signal processing device according tothe present embodiment is described below.

[0052] First, the analog input signal 2 is supplied as input to the A/Dconverter 1 d from the internal system 5 d. The A/D converter 1 doutputs the digital output signal 3 according to the analog input signal2. At the same time, the internal system characteristic 7 is supplied asinput to the system characteristic monitor 8 from the internal system 5d. Upon receiving the internal system characteristic 7, the systemcharacteristic monitor 8 outputs the control signal 4 to the A/Dconverter id. Meanwhile, the digital output signal 3 is fed back to theinternal system 5 d. The internal system 5 d again outputs the internalsystem characteristic 7 according to the digital output signal 3, andsupplies this as input to the system characteristic monitor 8. At thistime, the power consumption of the A/D converter 1 d is controlled bythe control signal 4 that is supplied from the system characteristicmonitor 8. The power consumption and performance of the A/D converter 1d are approximately correlated to each other, and therefore, theperformance of the A/D converter 1 d can be changed by controlling thepower consumption of the A/D converter 1 d.

[0053] Thus, according to the present embodiment, the performance of theA/D converter 1 d can be reduced to the minimum level that is requiredby the overall system by monitoring the system performance that variesaccording to the performance of the A/D converter 1 d. Therefore, it ispossible to optimize the power consumption and performance of the A/Dconverter 1 d and reduce the power consumption of the overall system.

[0054] Embodiment 5

[0055]FIG. 5 is a diagram showing the configuration of a signalprocessing device according to Embodiment 5 of the present invention.This signal processing device can be used, for example, for such casesthat a radio wave signal containing video and audio information isreceived, and then the received radio wave signal is subjected to A/Dconversion and digitally demodulated, such as in digital televisions orthe like.

[0056] In FIG. 5, reference character 1 e indicates an A/D converter;reference character 9 indicates a digital demodulator circuit serving asa signal processing means, in which part of the performance isdetermined by the resolution of the A/D converter 1 e; referencecharacter 6 e indicates an external system that incorporates the A/Dconverter Id and the digital demodulator circuit 9 inside; and referencecharacter 11 indicates a bit error rate monitor serving as a monitoringmeans. The bit error rate monitor 11 monitors the performance of thedigital demodulator circuit 9 attributable to the resolution of the A/Dconverter 1 e, and instructs the A/D converter to increase theresolution if a decrease of the performance is detected and instructsthe A/D converter to reduce the resolution if an overhead of theperformance is detected

[0057] An analog input signal that is supplied to the external system 6e is supplied as input to the A/D converter 1 e. The A/D converter 1 eoutputs a digital output signal 3 according to the analog input signal2. The resulting digital output signal 3 is supplied to the digitaldemodulator circuit 9. Meanwhile, the bit error rate 10 is supplied fromthe digital demodulator circuit 9 to the bit error rate monitor 11. Thebit error rate monitor 11 outputs a control signal 4. The control signal4 is supplied to the A/D converter 1 e. The signal processing systemaccording to Embodiment 5 of the present invention is thus configured.

[0058] Next, the operation of the signal processing device according tothe present embodiment is described below.

[0059] First, the analog input signal 2 that is supplied to the externalsystem 6 e is supplied as input to the A/D converter 1 e. The A/Dconverter 1 e outputs the digital output signal 3 according to theanalog input signal 2. The digital output signal 3 is supplied to thedigital demodulator circuit 9. The digital demodulator circuit 9performs digital demodulation and error correction according to thedigital output signal 3. By performing the error correction, a bit errorrate 10 is obtained from the digital demodulator circuit 9. The biterror rate 10 changes according to the status of radio wave receptionand the performance of the A/D converter 1 e. In other words, if thestatus of radio wave reception degrades or if the performance of the A/Dconverter decreases, the bit error rate 10 deteriorates. If the biterror rate 10 deteriorates, the bit error monitor 11 outputs the controlsignal 4 such that the power consumption of the A/D converter 1 eincreases, until the bit error rate 10 reaches a predetermined value. Onthe other hand, if the bit error rate 10 improves, the bit error monitor11 outputs the control signal 4 such that the power consumption of theA/D converter 1 e reduces, until the bit error rate 10 reaches thepredetermined value. Next, the resulting control signal 4 is supplied tothe A/D converter 1 e. At this time, the power consumption of the A/Dconverter 1 e is controlled by the control signal 4. The powerconsumption and performance of the A/D converter 1 e are approximatelycorrelated to each other, and therefore, the performance of the A/Dconverter 1 e can be changed by controlling the power consumption of theA/D converter 1 e.

[0060] Thus, according to the present embodiment, it is possible toreduce the performance of the A/D converter 1 e to the minimum levelthat is required by the digital demodulator circuit 9 by monitoring thebit error rate 10 that is output from the digital demodulator circuit 9.Therefore, the power consumption and performance of the A/D converter 1e can be optimized, and the power consumption of the overall system canbe reduced.

[0061] Embodiment 6

[0062]FIG. 6 shows a differential input-differential output operationalamplifier 12 a as an example of the operational amplifier incorporatedin an A/D converter according to Embodiment 6.

[0063] In FIG. 6, reference character Iss indicates a variable currentsource, reference characters M1 and M2 indicate N-channel transistors,and M3 and M4 indicate P-channel transistors.

[0064] It should be noted that, in an A/D converter, an operationalamplifier is mainly used as a sample-and-hold circuit, a voltagecomparator, and a circuit for adjusting the input range between thestages in a pipeline A/D converter or in a subranging A/D converter.

[0065] One end of the variable current source Iss is connected to areference voltage VSS, while the other end is connected to the sourceterminals of the N-channel transistors M1 and M2. The gate terminals ofthe N-channel transistors M1 and M2 are respectively connected an analogdifferential input signal-positive electrode Vin⁺ and an analogdifferential input signal-negative electrode Vin⁻. The gate terminals ofthe P-channel transistors M3 and M4 are connected a bias voltage Vb. Thesource terminals of the P-channel transistors M3 and M4 are connected toa power supply voltage VDD. The drain terminals of the N-channeltransistor M1 and the P-channel transistor M3 are respectively connectedan analog differential output signal-negative electrode Vout⁻, whereasthe drain terminals of the N-channel transistor M2 and the P-channeltransistor M4 are respectively connected an analog differential outputsignal-positive electrode Vout⁺. The operational amplifier 12 aincorporated in the A/D converter according to Embodiment 6 of theinvention is thus configured.

[0066] Next, the operation of the operational amplifier 12 aincorporated in the A/D converter according to the present embodiment isdescribed below.

[0067] Where an analog differential input signal is ΔVin=(Vin⁺−Vin⁻) andan analog differential output signal is ΔVout=(ΔVout⁺−ΔVout⁻), a voltagegain G of the present circuit is obtained by the following equation:G=ΔVout/ΔVin=gm·ro, as described previously. In other words, the voltagegain G of the operational amplifier 12 a is proportional to thetransconductance gm of the N-channel transistors M1 and M2, which areinput transistors. The transconductance gm is approximately proportionalto the drain-source current Ids flowing in the N-channel transistors M1and M2. In the above equations, gm=gm1=gm2, where gm1 denotes thetransconductance of the N-channel transistor M1, and gm2 denotes thetransconductance of the N-channel transistor M2. In addition, ro denotesthe dynamic resistance of the output terminal.

[0068] As the variable current source Iss is increased, the drain-sourcecurrents Ids1 and Ids2 increase. On the other hand, as the variablecurrent source Iss is reduced, the drain-source currents Ids1 and Ids2decrease. Therefore, when the variable current source Iss is increased,the voltage gain G increases, whereas when the variable current sourceIss is reduced, the voltage gain G decreases.

[0069] The increase or decrease of the voltage gain G causes acorresponding increase or decrease of the frequency band characteristicand the offset error characteristic of the operational amplifier 12 a.In other words, the characteristics of the operational amplifier 12 acan be correspondingly varied by changing the variable current sourceIss, and as a consequence, the performance of the A/D converter is alsovaried correspondingly.

[0070] Thus, the power consumption and performance of the A/D convertercan be controlled by making the current flowing through the operationalamplifier 12 a used in the A/D converter variable.

[0071] It should be noted that the present embodiment has described theoperational amplifier in which the input terminal is the gate terminalof the N-channel transistor, but of course, similar effects can beobtained for the operational amplifier in which the input terminal isthe gate terminal of the P-channel transistor.

[0072] Moreover, it should be noted that the present embodiment hasdescribed a simple differential input-differential output operationalamplifier, but similar effects can be obtained for current-biased typeoperational amplifies that are differential input-single outputoperational amplifiers, single input-single output operationalamplifiers, single input-differential output operational amplifiers, andeven more complicated operational amplifiers.

[0073] In addition, a configuration as shown in FIG. 7 is also possible.In this configuration, an N-channel transistor M0 a and an N-channeltransistor M0 b form a current mirror circuit to make the current Issain the bias circuit variable. In the configuration of FIG. 7, thecurrent Issb flowing through the N-channel transistor M0 b is such thata variable current source output Issa is multiplied by the currentmirror ratio. The current Issb then becomes the bias current of theoperational amplifier 12 b, and consequently, similar effects to thosedescribed above can be obtained.

[0074]FIG. 7 shows that N-channel transistors are used for forming thecurrent mirror circuit. However, depending on circuit configurations, itis also possible to form a current mirror circuit using P-channeltransistors. In addition, although FIG. 7 shows a single type currentmirror circuit, a cascade type current mirror circuit can attain similareffects to those described above.

[0075] The variable current supply Iss shown in FIGS. 6 and 7 can beattained by a circuit as shown in FIG. 8. As shown in FIG. 8, one end ofthe constant current source Issa is connected to a reference voltageVDD, whereas the other end is connected to the drain terminal and thegate terminal of an N-channel transistor M0 a. The source terminal ofthe N-channel transistor M0 a is connected to the reference voltage VSS.The source terminals of N-channel transistors M0 b 1 to M0 bn areconnected to the reference voltage VSS, whereas the drain terminalsthereof are connected to each other. The gate terminals of the N-channeltransistors M0 b 1 to M0 bn are connected to output terminals C ofswitches SW1 to SWn. An input terminal A of each of the switches SW1 toSWn is connected to the gate terminal and the drain terminal of theN-channel transistor M0 a. An input terminal B of each of the switchesSW1 to SWn is connected to the reference voltage VSS. By bringing theinput terminal A and the output terminal C of the switch SW1 into aconductive state, the N-channel transistor M0 a and the N-channeltransistor M0 bi form a current mirror circuit. Thus, current Issbi,which is the current Issa that is multiplied by the current mirrorratio, flows between the drain and the source of the N-channeltransistor M0 bi. On the other hand, by brining the input terminal B andthe output terminal C of the switch SWi, the N-channel transistor M0 biis switched to an OFF state and current does not flow between the drainand the source. By selecting the input terminal A or the input terminalB in each of the switches SW1 to SWn with the control signal 4, it ispossible to determine the variable current source Iss is to be any oneof Issb1 to Issbn or the combinations thereof, or to be 0. With thisconfiguration, it is possible to attain the variable current source Iss.

[0076] It should be noted that, although FIG. 8 describes a currentmirror circuit that is constructed using N-channel transistors, similareffects to those described above can be obtained by constructing acurrent mirror circuit using P-channel transistors.

[0077] Embodiment 7

[0078]FIG. 9 is a diagram showing an example of the operationalamplifier incorporated in an A/D converter according to Embodiment 7 ofthe present invention. Reference character 12 b denotes a differentialinput-differential output operational amplifier, reference characters M0a, M0 b, M1, and M2 denote N-channel transistors, reference charactersM3 and M4 denote P-channel transistors, reference character 4 denotes acontrol signal, and reference character 13 denotes a current output typeD/A converter.

[0079] The control signal 4 is input to the D/A converter 13. TheN-channel transistors M0 a and M0 b form a current mirror circuit. Thesource terminal of the N-channel transistor M0 b is connected to areference voltage VSS. The drain terminal thereof is connected to thesource terminals of the N-channel transistors M1 and M2. The gateterminals of the N-channel transistors M1 and M2 are respectivelyconnected to an analog differential input signal-positive electrode Vin⁺and an analog differential input signal-negative electrode Vin⁻. Thegate terminals of the P-channel transistors M3 and M4 are connected to abias voltage Vb. The source terminals of the P-channel transistors M3and M4 are connected to a power source voltage VDD. The drain terminalsof the N-channel transistor M1 and the P-channel transistor M3 areconnected to the analog differential output signal-negative electrodeVout⁻. The drain terminals of the N-channel transistor M2 and theP-channel transistor M4 are connected to the analog differential outputsignal-positive electrode Vout⁺. The operational amplifier 12 bincorporated in the A/D converter according to Embodiment 7 is thusconfigured.

[0080] Next, the operation of the operational amplifier 12 bincorporated in the A/D converter according to the present embodiment isdescribed below.

[0081] First, the control signal 4 is supplied to the D/A converter 13.The D/A converter 13 outputs a current lout that is uniquely determinedfor the control signal 4. The output current lout flows from the drainterminal of the N-channel transistor M0 a into the reference voltageVSS. Since the N-channel transistors M0 a and M0 b form a current mirrorcircuit, a current Issb, which the current Issa that is multiplied bythe current mirror ratio, flows from the drain terminal of the N-channeltransistor M0 b into the reference voltage VSS. The current Issb becomesthe bias current of the operational amplifier 12 b.

[0082] Thus, according to the present embodiment, it is made possible tocontrol the current that flows in the operational amplifier 12 bincorporated in the A/ID converter according to the control signal 4input to the D/A converter 13, according to the gradation of the D/Aconverter 13. As a result, the power consumption and performance of theA/D converter can be controlled.

[0083] The present embodiment describes a current output D/A converter,but a voltage output D/A converter can also attain similar effects tothose described above by performing voltage-current conversion using aresistive load.

[0084] Embodiment 8

[0085]FIG. 10 is a diagram showing an A/D converter according toEmbodiment 8 of the present invention.

[0086] In FIG. 10, reference character 16 denotes a control circuitserving as a controlling means that determines a resolution, referencecharacter 12 c denotes an operational amplifier that changes currentwith a signal from the control circuit 16, reference character 14denotes a voltage comparator array to which an output from theoperational amplifier 12 c is input. This A/D converter is so configuredthat the resolution is corrected by inputting the result of comparisonin the voltage comparator array 14 into the control circuit 16. Theoperational amplifier 12 c of the A/D converter is supplied as testvoltage with an input voltage signal Vinp and an input voltage signalVinn. The voltage comparator array 14 receives as input an outputvoltage signal Vout from the operational amplifier 12 c and outputs avoltage comparator array output 15. The control circuit 16 receives asinput the voltage comparator array output 15 and a control signal 4 a. Acontrol signal 4 b, which is the output from the control circuit 16, issupplied to the operational amplifier 12 c. The A/D converter accordingto Embodiment 8 is thus configured. The A/D converter according to thepresent embodiment is such that it determines the amount of currentflowing through the operational amplifier 12 c during an initialoperation period.

[0087] Next, the operation of the A/D converter according to the presentembodiment is described with reference to FIG. 11 showing a timing chartand FIG. 12 showing a detailed illustration of the voltage comparatorarray 14.

[0088] First, it should be noted that the initial operation period ofthe A/D converter that the system requires corresponds to a periodduring which a signal Initialize shown in FIG. 11 is high. During theinitial operation period, an input signal (Vinp−Vinn) is changed from V1to V2 in synchronization with Clock. Additionally, when an input voltageis V1, a sufficient settling time (a period from A to B in FIG. 11) isgiven to the operational amplifier 12 c.

[0089] Next, the input voltage is changed to V2. However, a current ILleaks a little to a load capacitance CL that is present at the outputend of the operational amplifier 12 c, and for this reason, an outputvoltage signal Vout from the operational amplifier 12 c does notimmediately change to the voltage level V2 but changes gradually asshown in FIG. 11. Then, a sampling is performed at the operation timing(indicated by C in FIG. 11) at which A/D conversion is carried out.Where the voltage level of the output voltage signal Vout at this pointis V2′, a settling error is represented by V2−V2′. The term “settingerror” herein means the difference between a voltage level V2 and anoutput voltage level V2′ that is actually output. Under this condition,voltage levels Va to Vd are compared with the voltage level V2′, usingcomparators Co1 to Co4. It should be noted that the voltage levels Va toVd are levels that correspond to the errors 1LSB/2, 2LSB/2, 4LSB/2, and8LSB/2, respectively, when the voltage level V2 is an ideal value.

[0090] The settling error is detected with the voltage comparator arrayoutput 15. On the other hand, the control signal 4 a has informationabout the precision of the operational amplifier that is necessary toconstruct an A/D converter having a certain precision, which is suppliedto the controlling circuit 16. Generally, the settling error iscorrelated to the reciprocal of the current flowing through theoperational amplifier 12 c. Specifically, the larger the current flowingthrough the operational amplifier 12 c is, the less the settling error,and conversely, the smaller the current flowing through the operationalamplifier 12 c is, the greater the settling error. Then, based on thevoltage comparator array output 15, it is detected if the settling errorat that time falls under 1LSB/2, 2LSB/2, 4LSB/2, or 8LSB/2. For example,when b1 and b2 are high and b3 and b4 are low, the settling error isbetween 4LSB/2 and 2LSB/2.

[0091] Here, when the settling error is larger than a required precisionof the operational amplifier 12 c that is specified by the controlsignal 4 a and the required precision is not met, a control signal 4 bis supplied from the controlling circuit 16 to the operational amplifier12 c such that the current flowing through the operational amplifier 12c is increased. As a consequence, the operation that is performed duringthe period from time A to time C shown in FIG. 11 is repeated. On theother hand, when the settling error is sufficiently small and therequired precision specified by the control signal 4 a is sufficientlymet, the control signal 4 b is supplied from the controlling circuit 16to the operational amplifier 12 c such that the current flowing throughthe operational amplifier 12 c is reduced. As a consequence, theoperation that is performed during the period from time A to time Cshown in FIG. 11 is repeated. Further, when the settling error fallswithin the required precision of the operational amplifier 12 c that isspecified by the control signal 4 a, the initial operation is ended.

[0092] According to the present embodiment, the precision of theoperational amplifier 12 c is detected from the settling error of theoperational amplifier 12 c, and the current in the operational amplifier12 c is controlled according to the control signal 4 a such as to obtainthe precision of the operational amplifier 12 c that is necessary toachieve the precision of the A/D converter that is required by thesystem. Thus, it is possible to control the power consumption andperformance of the A/D converter.

[0093] As has been discussed thus far, according to the presentinvention, when the performance of an A/D converter that is required bya system changes, the current of the operational amplifier that isincorporated in the A/D converter is controlled by a control signal.Consequently, the present invention makes it possible to change thepower consumption and performance of the A/D converter corresponding tothe required performance. Thus, the power consumption and performance ofthe A/D converter can be optimized to the optimal operation conditionsaccording to the operation situation of the system, and the powerconsumption of the overall system can be reduced.

[0094] The invention may be embodied in other forms without departingfrom the spirit or essential characteristics thereof. The embodimentsdisclosed in this application are to be considered in all respects asillustrative and not limiting. The scope of the invention is indicatedby the appended claims rather than by the foregoing description, and allchanges which come within the meaning and range of equivalency of theclaims are intended to be embraced therein.

What is claimed is:
 1. An A/D converter wherein its resolution is madevariable by changing a current flowing through an amplifier with acontrol signal that specifies the resolution.
 2. A signal processingdevice comprising: the A/D converter according to claim 1; a signalprocessing means in which part of the performance is determined by theresolution of the A/D converter; a monitoring means for monitoring theperformance of the signal processing means attributable to theresolution of the A/D converter and instructing the A/D converter toincrease the resolution if a decrease of the performance is detected andto reduce the resolution if an overhead of the performance is detected.3. The signal processing device according to claim 2, wherein: thesignal processing means is a digital demodulator circuit; and theperformance is a bit error rate of the digital demodulator circuit. 4.An A/D converter comprising: a controlling means for determining aresolution; an amplifier for changing a current with a signal from thecontrolling means; and a voltage comparator array to which an outputfrom the amplifier is input; wherein the resolution is corrected byinputting the result of the comparison in the voltage comparator arrayinto the controlling means.
 5. A signal processing device comprising: anA/D converter according to claim 4; a signal processing means in whichpart of the performance is determined by the resolution of the A/Dconverter; and a monitoring means for monitoring the performance of thesignal processing means attributable to the resolution of the A/Dconverter and instructing the A/D converter to increase the resolutionif a decrease of the performance is detected and to reduce theresolution if an overhead of the performance is detected.
 6. The signalprocessing device according to claim 5, wherein: the signal processingmeans is a digital demodulator circuit; and the performance is a biterror rate of the digital demodulator circuit.
 7. A method of A/Dconversion, comprising: a voltage-inputting step of inputting a testvoltage in an amplifier; a comparing step of comparing the voltage thatis output from the amplifier with the test voltage; and aresolution-determining step of adjusting a current value of theamplifier according to the result obtained in the comparing step.